FIELD OF THE INVENTION
The invention relates to a field-effect-controllable, vertical semiconductor component, including a semiconductor body, at least one drain zone of a first conduction type, at least one source zone of the first conduction type, at least one gate electrode insulated from the entire semiconductor body by a gate oxide, and a bulk region of the first conduction type. The invention also relates to a method for producing a field-effect-controllable, vertical semiconductor component.
Field-effect-controllable semiconductor components of that kind are, for example, MOS field-effect transistors (MOSFETs) Such MOSFETs have been known for a long time and are described, for example, in the Siemens-Datenbuch [Data Manual] 1993/94 SIPMOS-Halbleiter, Leistungstransistoren und Dioden [SIPMOS Semiconductors, Power Transistors and Diodes], pp. 29 ff. FIG. 4 on page 30 of that data manual shows the basic layout of a power transistor of that kind. The transistor shown there is a vertical n-channel SIPMOS transistor. In such a transistor, the n.sup.+ substrate serves as a carrier with the drain metallizing beneath it. Above the n.sup.+ substrate, an n-epitaxial layer follows, which is variously thick and correspondingly doped depending on the depletion voltage. The gate over that, made of n.sup.+ polysilicon, is embedded in insulating silicon dioxide and acts as an implantation mask for the p well and the n.sup.+ source zone. The source metallizing covers the entire structure and connects the individual transistor cells of the chip in parallel. Further details of that vertically constructed power transistor can be found on pages 30 ff. of the aforementioned data manual.
A disadvantage of such a configuration is that the on-state resistance R.sub.on of the drain-to-source load path increases with increasing dielectric strength of the semiconductor component, since the thickness of the epitaxial layer necessarily increases. At 50V, the on-state resistance R.sub.on per unit of surface area is approximately 0.20 .OMEGA.mm.sup.2, and rises at a depletion voltage of 1000V to a value of approximately 10 .OMEGA.mm.sup.2,for instance.
In contrast to lateral MOSFETs, vertical MOSFETs have a substantially vertical current flow direction. That causes the current to flow from the front side of the wafer to the rear side of the wafer. In vertical MOSFETs of that generic type, the source and gate terminals are located on the front side of the wafer, while the drain terminal is contacted through the rear side of the wafer. As a result, vertical MOSFETs have the advantage over lateral MOSFETs of being integratable on the semiconductor chip in a space-saving way, and therefore the components can be manufactured less expensively.
Vertical MOSFETs are typically secured by the rear side of the wafer to a cooling body or to the device housing. One disadvantage of such a configuration is that an insulating layer must be applied between the drain rear side contact and the cooling body, which typically is at the potential of the device ground. The insulating layer increases the heat resistance between the drain rear side contact and the cooling body. That leads to reduced heat dissipation through the rear side of the wafer.